1. Field of the Invention
The present invention generally concerns electronic power conversion circuits and, more particularly, concerns current mode control circuits for power converters.
2. Background of the Invention
Current mode control schemes for power converters provide numerous advantages over other control schemes. These advantages include good dynamic behavior with a simple compensation network, rejection of the disturbance caused by the input voltage, inherent pulse-by-pulse overcurrent protection, and ease of implementation of current sharing. FIG. 1 is a diagram of a power converter 10, in this case a buck converter, with a conventional analog current mode control circuit 12. The power switch 14 of the buck converter 10 is turned on by the pulse created by the clock 16 of the current mode control circuit and turned off when the signal of the current monitor 18 exceeds the threshold level programmed by the voltage feedback loop compensator 20 via a flip-flop 22. This type of control scheme is known as peak current mode control. Numerous variations of such analog peak current mode control circuits are known and used throughout the power conversion industry.
Technological progress on both the demand side and the supply side, however, creates significant incentive to implement increasing portions of the controller with digital circuitry. Digital circuitry provides the advantages of programmability, stability, noise immunity and ability to implement complex timing and signal processing operations. In that connection, economies of engineering naturally entice designers to replicate the analog structure and techniques that work well in analog technology with digital circuitry. The straightforward replication of the analog current mode control circuit 12 of FIG. 1 with digital means, as shown in FIG. 2, however, leads to serious difficulty. In the digital current mode control circuit 24 of FIG. 2, the temporal resolution achievable is dictated by the repetition rate of the sampling and A/D conversion circuitry 26. Resolution necessary to suppress quantization noise to a level that does not have a detrimental effect on the overall performance of the power converter 10 implies sampling every few nanoseconds for typical point-of-load (POL) converters and perhaps as low as one nanosecond for high performance designs. A/D converters capable of meeting such requirements are prohibitively expensive for most applications. Also, operating an A/D converter with a low sampling frequency leads to a phenomenon known as limit cycle oscillation, which in turn introduces complex, non-linear oscillations of the output voltage. These oscillations are typically bounded in nature and may be acceptable for some applications. In some cases, however, they cause an interaction with the voltage control loop. The non-linear nature of limit cycle oscillation that causes such interaction is difficult to analyze and, as such, compromises the reliability of the converter.
Accordingly, there exists a need for a digital current mode control circuit that can operate at low sampling frequencies without experiencing the drawbacks associated with limit cycle oscillation.